OpenCL kernels are programs that execute across various CPU, GPU and FPGA platforms. Vivado 2014.1 introduced support for automatically converting OpenCL kernels to IP for Xilinx devices. Vivado HLS is widely reviewed to increase developer productivity, and is confirmed to support C++ classes, templates, functions and operator overloading. The Vivado High-Level Synthesis compiler enables C, C++ and SystemC programs to be directly targeted into Xilinx devices without the need to manually create RTL. A free version WebPACK Edition of Vivado provides designers with a limited version of the design environment.
Vivado includes electronic system level (ESL) design tools for synthesizing and verifying C-based algorithmic IP standards based packaging of both algorithmic and RTL IP for reuse standards based IP stitching and systems integration of all types of system building blocks and the verification of blocks and systems. Vivado was introduced in April 2012, and is an integrated design environment (IDE) with system-to-IC level tools built on a shared scalable data model and a common debug environment. Replacing the 15 year old ISE with Vivado Design Suite took 1000 man-years and cost US$200 million. Vivado also introduces high-level synthesis, with a toolchain that converts C code into programmable logic. Like the later versions of ISE, Vivado includes the in-built logic simulator. Vivado represents a ground-up rewrite and re-thinking of the entire design flow (compared to ISE). Vivado Design Suite is a software suite produced by Xilinx for synthesis and analysis of hardware description language (HDL) designs, superseding Xilinx ISE with additional features for system on a chip development and high-level synthesis.
WebPACK Edition: no-cost for selected (smaller) devices
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